1. Field of the Invention
The present invention is directed generally to a memory device and, more particularly, to a memory device having two or more memory arrays and a testpath operably connected to one of the memory arrays and not operably connected to another of the memory arrays. The present invention is also directed to a method of operating the testpath.
2. Description of the Background
Memory devices, such as random access memories ("RAMs"), often include more than one memory array. For example, a memory device may include two separate memory arrays that are collectively used by the memory device to store data. One advantage of such a device is that it offers a potential for lower power consumption. For example, one of the memory arrays may be placed in an inactive or low power mode when that memory array is not expected to be used for a period of time. As a result, the power consumed by the device is significantly reduced.
Memory arrays also typically include one or more datapaths from the memory arrays, in which data is stored, to output terminals or DQ pads, through which data signals are provided to and retrieved from the memory arrays. A datapath will selectively provide one or more data signals from the memory arrays to the DQ pads. The particular data signal selected by the datapath depends on the memory address selected. The memory address, or data derived therefrom, is used by the datapath to select desired data signals.
Most memory arrays also typically include a number of redundant memory elements that may be logically substituted for malfunctioning memory elements. That substitution is typically accomplished by remapping the memory device so that read and write operations directed towards a malfunctioning memory element are redirected to a redundant memory element. It is determined which memory elements, if any, are malfunctioning and need to be replaced by testing the memory device. Testing typically involves writing a known pattern of data to the memory device, internally retrieving data from the memory arrays and internally compressing the data, reading the compressed data from the memory device, and comparing the compressed data to a known compressed data pattern. If a malfunctioning memory element is discovered, it may be logically replaced with redundant memory.
Prior art memory devices, however, suffer from shortcomings. For example, if an error indicative of a malfunctioning memory element is detected, prior art memory devices cannot determine which memory array contains the error. As a result, redundant memory is remapped in both memory arrays, even though an error may be present in only one of the memory arrays. As a result, prior art memory devices use redundant memory inefficiently, thereby reducing the number of defective memory elements that can be replaced in a memory device, and thereby reducing yield and increasing costs.
Some prior art designs having two memory arrays can determine which of the memory arrays contains a defective memory element. Those designs, however, require that both memory arrays remain powered up during normal operation, thereby resulting in increased power consumption when compared with memory devices that power down one or more memory array.
Accordingly, the need exists for a memory device that uses redundant memory in a more efficient manner. More particularly, the need exists for a memory device that can determine which one of several memory arrays contains a malfunctioning memory element. Similarly, the need exists for a memory device that does not require redundant memory to be used in both memory arrays when an error exists in only one of those arrays. Furthermore, the need exists for a memory device that also provides for reduced power consumption, for example, by powering down one or more of the memory arrays that are not in use.